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Jen-Wei Lee

Efficient Hardware Architecture of \eta_T Pairing Accelerator Over Characteristic Three
A 3.40 ms/GF (p521) and 2.77 ms/GF (2521) DF-ECC processor with side-channel attack resistance
Efficient power-analysis-resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture
Processor with side-channel attack resistance
A high-performance elliptic curve cryptographic processor over GF (p) with SPA resistance
An efficient countermeasure against correlation power-analysis attacks with randomized montgomery operations for DF-ECC processor

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